/***************************************************************************
*   Copyright (C) 2010-2011 by swkyer <swkyer@gmail.com>                  *
*                                                                         *
*   This program is free software; you can redistribute it and/or modify  *
*   it under the terms of the GNU General Public License as published by  *
*   the Free Software Foundation; either version 2 of the License, or     *
*   (at your option) any later version.                                   *
*                                                                         *
*   This program is distributed in the hope that it will be useful,       *
*   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
*   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
*   GNU General Public License for more details.                          *
*                                                                         *
*   You should have received a copy of the GNU General Public License     *
*   along with this program; if not, write to the                         *
*   Free Software Foundation, Inc.,                                       *
*   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
***************************************************************************/
#include "stdafx.h"
#include "mips32opc.h"


const ubase_t mips32_microcode_probe[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui		$15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori		$15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw		$1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw		$2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw		$3, 0($15)

	// Hosted virtual ram base address
	MIPS32_LUI(1, 0xFF2F),			// lui		$1, 0xFF2F
	MIPS32_ORI(1, 1, 0x8000),		// ori		$1, $1, 0x8000

	// commit access
	// sync
	MIPS32_NOP,

	// Read Cp0 Registers
	MIPS32_MFC0(2, 15, 0),			// mfc0		$2, $15			# cp0.prid
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 0, 1),				// sw		$2, 0($1)
	MIPS32_NOP,						// nop
	MIPS32_MFC0(3, 16, 0),			// mfc0		$3, $16			# cp0.config.0
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 4, 1),				// sw		$3, 4($1)
	MIPS32_NOP,						// nop
	MIPS32_MFC0(2, 16, 1),			// mfc0		$2, $16, 1		# cp0.config.1
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 8, 1),				// sw		$2, 8($1)
	MIPS32_NOP,						// nop
	MIPS32_MFC0(2, 16, 2),			// mfc0		$3, $16, 2		# cp0.config.2
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 12, 1),			// sw		$3, 12($1)
	MIPS32_NOP,						// nop
	MIPS32_MFC0(2, 16, 3),			// mfc0		$2, $16, 3		# cp0.config.3
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 16, 1),			// sw		$2, 16($1)
	MIPS32_NOP,						// nop
	MIPS32_MFC0(2, 23, 0),			// mfc0		$3, $23			# cp0.debug
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 20, 1),			// sw		$3, 20($1)
	MIPS32_NOP,						// nop

	MIPS32_LUI(2, 0xFF30),			// lui	    $2, 0xFF30
	MIPS32_LW(3, 0, 2),				// lw		$3, 0($2)		# DCR in drseg
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 24, 1),			// sw		$3, 24($1)
	MIPS32_NOP,						// nop
	MIPS32_LW(3, 0x1000, 2),		// lw		$3, 0x1000($2)	# IBS in drseg
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 28, 1),			// sw		$3, 28($1)
	MIPS32_NOP,						// nop
	MIPS32_LW(3, 0x2000, 2),		// lw		$3, 0x2000($2)	# DBS in drseg
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 32, 1),			// sw		$3, 32($1)
	MIPS32_NOP,						// nop

	// Pop from the debug stack
//pop_debug_stack:
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(52)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readregisters[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31

	MIPS32_LUI(15, 0xFF2F),			// lui		$15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFE00),		// ori	    $15, $15, 0xFE00

	MIPS32_SW(0, 0, 15),			// sw		$0, 0($15)
	MIPS32_SW(1, 4, 15),			// sw		$1, 4($15)
	MIPS32_SW(2, 8, 15),			// sw		$2, 8($15)

	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31
	MIPS32_MTC0(1, 31, 0),			// mtc0		$1,  $31

	// Load the pseudo stack address and push R2
	MIPS32_LUI(1, 0xFF2F),			// lui		$1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFFFC),		// ori	    $1, $1, 0xFFFC
	MIPS32_SW(2, 0, 1),				// sw		$2, 0($1)

	// Load the address to resume at
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFE0C),		// ori	    $1, $1, 0xFE0C

	MIPS32_SW(3, 0, 1),				// sw	    $3, 0($1)
	MIPS32_SW(4, 4, 1),				// sw	    $4, 4($1)
	MIPS32_SW(5, 8, 1),				// sw	    $5, 8($1)
	MIPS32_SW(6, 12, 1),			// sw	    $6, 12($1)
	MIPS32_SW(7, 16, 1),			// sw	    $7, 16($1)
	MIPS32_SW(8, 20, 1),			// sw	    $8, 20($1)
	MIPS32_SW(9, 24, 1),			// sw	    $9, 24($1)
	MIPS32_SW(10, 28, 1),			// sw	    $10, 28($1)
	MIPS32_SW(11, 32, 1),			// sw	    $11, 32($1)
	MIPS32_SW(12, 36, 1),			// sw	    $12, 36($1)
	MIPS32_SW(13, 40, 1),			// sw	    $13, 40($1)
	MIPS32_SW(14, 44, 1),			// sw	    $14, 44($1)
	MIPS32_SW(15, 48, 1),			// sw	    $15, 48($1)
	MIPS32_SW(16, 52, 1),			// sw	    $16, 52($1)
	MIPS32_SW(17, 56, 1),			// sw	    $17, 56($1)
	MIPS32_SW(18, 60, 1),			// sw	    $18, 60($1)
	MIPS32_SW(19, 64, 1),			// sw	    $19, 64($1)
	MIPS32_SW(20, 68, 1),			// sw	    $20, 68($1)
	MIPS32_SW(21, 72, 1),			// sw	    $21, 72($1)
	MIPS32_SW(22, 76, 1),			// sw	    $22, 76($1)
	MIPS32_SW(23, 80, 1),			// sw	    $23, 80($1)
	MIPS32_SW(24, 84, 1),			// sw	    $24, 84($1)
	MIPS32_SW(25, 88, 1),			// sw	    $25, 88($1)
	MIPS32_SW(26, 92, 1),			// sw	    $26, 92($1)
	MIPS32_SW(27, 96, 1),			// sw	    $27, 96($1)
	MIPS32_SW(28, 100, 1),			// sw	    $28, 100($1)
	MIPS32_SW(29, 104, 1),			// sw	    $29, 104($1)
	MIPS32_SW(30, 108, 1),			// sw	    $30, 108($1)
	MIPS32_SW(31, 112, 1),			// sw	    $31, 112($1)

	// STATUS REGISTER
	MIPS32_MFC0(2, 12, 0),			// mfc0		$2, $12
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 116, 1),			// sw	    $2, 116($1)
	MIPS32_NOP,						// nop

	// LO REGISTER
	MIPS32_MFLO(2),					// mflo		$2
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 120, 1),			// sw	    $2, 120($1)
	MIPS32_NOP,						// nop

	// HI REGISTER
	MIPS32_MFHI(2),					// mfhi		$2
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 124, 1),			// sw	    $2, 124($1)
	MIPS32_NOP,						// nop

	// BAD REGISTER
	MIPS32_MFC0(2, 8, 0),			// mfc0		$2, $8
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 128, 1),			// sw	    $2, 128($1)
	MIPS32_NOP,						// nop

	// CAUSE REGISTER
	MIPS32_MFC0(2, 13, 0),			// mfc0		$2, $13
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 132, 1),			// sw	    $2, 132($1)
	MIPS32_NOP,						// nop

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// PC REGISTER (DEPC)
	MIPS32_MFC0(2, 24, 0),			// mfc0		$2, $24
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 136, 1),			// sw	    $2, 136($1)
	MIPS32_NOP,						// nop

	// Now we need to reload R1 with the pseudo stack location and restore R2
//pop_debug_stack:
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFFFC),		// ori	    $1, $1, 0xFFFC
	MIPS32_LW(2, 0, 1),				// lw		$2, 0($1)

	// Restore R1 and we're done.
	MIPS32_MFC0(1, 31, 0),			// mfc0		$1, $31

	MIPS32_B(NEG16(73)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writeregisters[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFE00),		// ori	    $15, $15, 0xFE00

	MIPS32_SW(0, 0, 15),			// lw	    $0, 0($15)
	MIPS32_SW(1, 4, 15),			// lw	    $1, 4($15)
	MIPS32_SW(2, 8, 15),			// lw	    $2, 8($15)

	MIPS32_MTC0(1, 31, 0),			// mtc0		$1,  $31

	// Load the pseudo stack address and push R2
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFFFC),		// ori	    $1, $1, 0xFFFC
	MIPS32_SW(2, 0, 1),				// sw	    $2, 0($1)

	// Load the address to resume at
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFE0C),		// ori	    $1, $1, 0xFE0C

	MIPS32_LW(3, 0, 1),				// lw	    $3, 0($1)
	MIPS32_LW(4, 4, 1),				// lw	    $4, 4($1)
	MIPS32_LW(5, 8, 1),				// lw	    $5, 8($1)
	MIPS32_LW(6, 12, 1),			// lw	    $6, 12($1)
	MIPS32_LW(7, 16, 1),			// lw	    $7, 16($1)
	MIPS32_LW(8, 20, 1),			// lw	    $8, 20($1)
	MIPS32_LW(9, 24, 1),			// lw	    $9, 24($1)
	MIPS32_LW(10, 28, 1),			// lw	    $10, 28($1)
	MIPS32_LW(11, 32, 1),			// lw	    $11, 32($1)
	MIPS32_LW(12, 36, 1),			// lw	    $12, 36($1)
	MIPS32_LW(13, 40, 1),			// lw	    $13, 40($1)
	MIPS32_LW(14, 44, 1),			// lw	    $14, 44($1)
	MIPS32_LW(15, 48, 1),			// lw	    $15, 48($1)
	MIPS32_LW(16, 52, 1),			// lw	    $16, 52($1)
	MIPS32_LW(17, 56, 1),			// lw	    $17, 56($1)
	MIPS32_LW(18, 60, 1),			// lw	    $18, 60($1)
	MIPS32_LW(19, 64, 1),			// lw	    $19, 64($1)
	MIPS32_LW(20, 68, 1),			// lw	    $20, 68($1)
	MIPS32_LW(21, 72, 1),			// lw	    $21, 72($1)
	MIPS32_LW(22, 76, 1),			// lw	    $22, 76($1)
	MIPS32_LW(23, 80, 1),			// lw	    $23, 80($1)
	MIPS32_LW(24, 84, 1),			// lw	    $24, 84($1)
	MIPS32_LW(25, 88, 1),			// lw	    $25, 88($1)
	MIPS32_LW(26, 92, 1),			// lw	    $26, 92($1)
	MIPS32_LW(27, 96, 1),			// lw	    $27, 96($1)
	MIPS32_LW(28, 100, 1),			// lw	    $28, 100($1)
	MIPS32_LW(29, 104, 1),			// lw	    $29, 104($1)
	MIPS32_LW(30, 108, 1),			// lw	    $30, 108($1)
	MIPS32_LW(31, 112, 1),			// lw	    $31, 112($1)

	// STATUS REGISTER
	MIPS32_LW(2, 116, 1),			// lw	    $2, 116($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 12, 0),			// mtc0		$2, $12
	MIPS32_NOP,						// nop

	// LO REGISTER
	MIPS32_LW(2, 120, 1),			// lw	    $2, 120($1)
	MIPS32_NOP,						// nop
	MIPS32_MTLO(2),					// mtlo		$2
	MIPS32_NOP,						// nop

	// HI REGISTER
	MIPS32_LW(2, 124, 1),			// lw	    $2, 124($1)
	MIPS32_NOP,						// nop
	MIPS32_MTHI(2),					// mthi		$2
	MIPS32_NOP,						// nop

	// BAD REGISTER
	MIPS32_LW(2, 128, 1),			// lw	    $2, 128($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 8, 0),			// mtc0		$2, $8
	MIPS32_NOP,						// nop

	// CAUSE REGISTER
	MIPS32_LW(2, 132, 1),			// lw	    $2, 132($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 13, 0),			// mtc0		$2, $13
	MIPS32_NOP,						// nop

	// PC REGISTER (DEPC)
	MIPS32_LW(2, 136, 1),			// lw	    $2, 136($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 24, 0),			// mtc0		$2, $24
	MIPS32_NOP,						// nop

	// commit access
	// sync
	MIPS32_NOP,						// nop

	// Now we need to reload R1 with the pseudo stack location and restore R2
//pop_debug_stack:
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFFFC),		// ori	    $1, $1, 0xFFFC
	MIPS32_SW(2, 0, 1),				// lw	    $2, 0($1)

	// Restore R1 and we're done.
	MIPS32_MFC0(1, 31, 0),			// mfc0		$1, $31

	MIPS32_B(NEG16(71)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readbyte[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 1),				// lw	    $2, 0($1)       # destination address
	MIPS32_NOP,						// nop

	MIPS32_LBU(3, 0, 2),			// lbu	    $3, 0($2)
	MIPS32_NOP,						// nop

	// Store the value into the data register
	MIPS32_SW(3, 4, 1),				// sw	    $3, 4($1)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(19)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readhalf[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)

	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 1),				// lw	    $2, 0($1)       # destination address
	MIPS32_NOP,						// nop

	MIPS32_LHU(3, 0, 2),			// lhu	    $3, 0($2)
	MIPS32_NOP,						// nop

	// Store the value into the data register
	MIPS32_SW(3, 4, 1),				// sw	    $3, 4($1)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(19)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readword[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)

	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 1),				// lw	    $2, 0($1)       # destination address
	MIPS32_NOP,						// nop

	MIPS32_LW(3, 0, 2),				// lw	    $3, 0($2)
	MIPS32_NOP,						// nop

	// Store the value into the data register
	MIPS32_SW(3, 4, 1),				// sw	    $3, 4($1)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(19)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writebyte[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 1),				// lw	    $2, 0($1)       # destination address
	MIPS32_LW(3, 4, 1),				// lw	    $3, 4($1)       # data
	MIPS32_NOP,						// nop

	// Store the byte at @R2 (the address)
	MIPS32_SB(3, 0, 2),				// sb	    $3, 0($2)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(19)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writehalf[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 1),				// lw	    $2, 0($1)       # destination address
	MIPS32_LW(3, 4, 1),				// lw	    $3, 4($1)       # data
	MIPS32_NOP,						// nop

	// Store the byte at @R2 (the address)
	MIPS32_SH(3, 0, 2),				// sh	    $3, 0($2)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(19)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writeword[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 1),				// lw	    $2, 0($1)       # destination address
	MIPS32_LW(3, 4, 1),				// lw	    $3, 4($1)       # data
	MIPS32_NOP,						// nop

	// Store the byte at @R2 (the address)
	MIPS32_SW(3, 0, 2),				// sw	    $3, 0($2)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(19)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readdebug[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Load R1 with the address of the data register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori	    $1, $1, 0xFD04

	// Load R2 with the debug register (CP0 reg 23 select 0)
	MIPS32_MFC0(2, 23, 0),			// mfc0		$2, $23, 0
	MIPS32_NOP,						// nop

	// Store R2 @R1 into the data register
	MIPS32_SW(2, 0, 1),				// sw	    $2, 0($1)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 23, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(17)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writedebug[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// Load R1 with the address of the data register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori	    $1, $1, 0xFD04

	// load R2 @R1 into the data register
	MIPS32_LW(2, 0, 1),				// lw	    $2, 0($1)
	MIPS32_NOP,						// nop

	// Store R2 to the debug register (CP0 reg 23 select 0)
	MIPS32_MTC0(2, 23, 0),			// mtc0		$2, $23, 0
	MIPS32_NOP,						// nop

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 23, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(17)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readdcr[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Load R1 with the address of the data register
	MIPS32_LUI(1, 0xFF30),			// lui		$1, 0xFF30
	MIPS32_LW(2, 0, 1),				// lw		$2, 0($1)
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori		$1, $1, 0xFD04
	MIPS32_SW(2, 0, 1),			// sw		$2, 0($1)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 23, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(17)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writedcr[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// Load R1 with the address of the data register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori	    $1, $1, 0xFD04
	MIPS32_SW(2, 0, 1),				// lw		$2, 0($1)
	MIPS32_LUI(1, 0xFF30),			// lui		$1, 0xFF30
	MIPS32_SW(2, 0, 1),				// sw		$2, 0($1)
	MIPS32_NOP,						// nop

	//sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 23, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(17)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_singlestepset[] = 
{
// start:
	// Store R1 in the debug scratch register
	MIPS32_MTC0(1, 31, 0),			// mtc0		$1, $31

	// commit access
	// sync
	MIPS32_NOP,						// nop

	// Load R1 with the debug register (CP0 reg 23 select 0)
	MIPS32_MFC0(1, 23, 0),			// mfc0		$1, $23
	MIPS32_NOP,						// nop

	// Set the SSt bit in the debug register
	MIPS32_ORI(1, 1, 0x0100),		// ori	    $1, $1, 0x0100

	// Put the modified debug register back
	MIPS32_MTC0(1, 23, 0),			// mtc0		$1, $23
	MIPS32_NOP,						// nop

	// commit access
	// sync
	MIPS32_NOP,						// nop

	// Restore R1 from the scratch register
//pop_debug_stack:
	MIPS32_MFC0(1, 31, 0),			// mfc0		$1, $31

	MIPS32_B(NEG16(12)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_singlestepclear[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Load R1 with the debug register (CP0 reg 23 select 0)
	MIPS32_MFC0(1, 23, 0),			// mfc0		$1, $23

	// Load the AND mask into R2
	MIPS32_LUI(2, 0xFFFF),			// lui	    $2, 0xFFFF
	MIPS32_ORI(2, 2, 0xFEFF),		// ori	    $2, $2, 0xFEFF

	// Clear the SSt bit in the debug register
	MIPS32_AND(1, 2, 2),			// and	    $1, $1, $2

	// Put the modified debug register back
	MIPS32_MTC0(1, 31, 0),			// mtc0		$1, $23
	MIPS32_NOP,						// nop

	// commit access
	// sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(19)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readcp0[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// Load R1 with the address of the first cp0 register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFF28),		// ori	    $1, $1, 0xFF28

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// cp0 index
	MIPS32_MFC0(2, 0, 0),			// mfc0		$2, $0
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 0, 1),				// sw		$2, 0($1)
	MIPS32_NOP,						// nop

	// cp0 random
	MIPS32_MFC0(2, 1, 0),			// mfc0		$2, $1
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 4, 1),				// sw	    $2, 4($1)
	MIPS32_NOP,						// nop

	// cp0 entrylo 0
	MIPS32_MFC0(2, 2, 0),			// mfc0		$2, $2
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 8, 1),				// sw	    $2, 8($1)
	MIPS32_NOP,						// nop

	// cp0 entrylo 1
	MIPS32_MFC0(2, 3, 0),			// mfc0		$2, $3
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 12, 1),			// sw	    $2, 12($1)
	MIPS32_NOP,						// nop

	// cp0 context
	MIPS32_MFC0(2, 4, 0),			// mfc0		$2, $4
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 16, 1),			// sw	    $2, 16($1)
	MIPS32_NOP,						// nop

	// cp0 pagemask
	MIPS32_MFC0(2, 5, 0),			// mfc0		$2, $5
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 20, 1),			// sw	    $2, 20($1)
	MIPS32_NOP,						// nop

	// cp0 wired
	MIPS32_MFC0(2, 6, 0),			// mfc0		$2, $6
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 24, 1),			// sw	    $2, 24($1)
	MIPS32_NOP,						// nop

	// cp0 reg7
	MIPS32_MFC0(2, 7, 0),			// mfc0		$2, $7
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 28, 1),			// sw	    $2, 28($1)
	MIPS32_NOP,						// nop

	// cp0 reg8
	MIPS32_MFC0(2, 8, 0),			// mfc0		$2, $8
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 32, 1),			// sw	    $2, 32($1)
	MIPS32_NOP,						// nop

	// cp0 reg9
	MIPS32_MFC0(2, 9, 0),			// mfc0		$2, $9
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 36, 1),			// sw	    $2, 36($1)
	MIPS32_NOP,						// nop

	// cp0 entryhi
	MIPS32_MFC0(2, 10, 0),			// mfc0		$2, $10
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 40, 1),			// sw	    $2, 40($1)
	MIPS32_NOP,						// nop

	// cp0 reg11
	MIPS32_MFC0(2, 11, 0),			// mfc0		$2, $11
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 44, 1),			// sw	    $2, 44($1)
	MIPS32_NOP,						// nop

	// cp0 reg12
	MIPS32_MFC0(2, 12, 0),			// mfc0		$2, $12
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 48, 1),			// sw	    $2, 48($1)
	MIPS32_NOP,						// nop

	// cp0 reg13
	MIPS32_MFC0(2, 13, 0),			// mfc0		$2, $13
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 52, 1),			// sw	    $2, 52($1)
	MIPS32_NOP,						// nop

	// cp0 reg14
	MIPS32_MFC0(2, 14, 0),			// mfc0		$2, $14
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 56, 1),			// sw		$2, 56($1)
	MIPS32_NOP,						// nop

	// cp0 prid
	MIPS32_MFC0(2, 15, 0),			// mfc0		$2, $15
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 60, 1),			// sw	    $2, 60($1)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(77)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writecp0[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// Load R1 with the address of the first cp0 register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFF28),		// ori	    $1, $1, 0xFF28

	// cp0 index
	MIPS32_SW(2, 0, 1),				// lw		$2, 0($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 0, 0),			// mtc0		$2, $0
	MIPS32_NOP,						// nop

	// cp0 random
	MIPS32_SW(2, 4, 1),				// lw      $2, 4($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 1, 0),			// mtc0    $2, $1
	MIPS32_NOP,						// nop

	// cp0 entrylo 0
	MIPS32_SW(2, 8, 1),				// lw      $2, 8($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 2, 0),			// mtc0    $2, $2
	MIPS32_NOP,						// nop

	// cp0 entrylo 1
	MIPS32_SW(2, 12, 1),			// lw      $2, 12($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 3, 0),			// mtc0    $2, $3
	MIPS32_NOP,						// nop

	// cp0 context
	MIPS32_SW(2, 16, 1),			// lw      $2, 16($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 4, 0),			// mtc0    $2, $4
	MIPS32_NOP,						// nop

	// cp0 pagemask
	MIPS32_SW(2, 20, 1),			// lw      $2, 20($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 5, 0),			// mtc0    $2, $5
	MIPS32_NOP,						// nop

	// cp0 wired
	MIPS32_SW(2, 24, 1),			// lw      $2, 24($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 6, 0),			// mtc0    $2, $6
	MIPS32_NOP,						// nop

	// cp0 reg7
	MIPS32_SW(2, 28, 1),			// lw      $2, 28($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 7, 0),			// mtc0    $2, $7
	MIPS32_NOP,						// nop

	// cp0 reg8
	MIPS32_SW(2, 32, 1),			// lw      $2, 32($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 8, 0),			// mtc0    $2, $8
	MIPS32_NOP,						// nop

	// cp0 reg9
	MIPS32_SW(2, 36, 1),			// lw      $2, 36($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 9, 0),			// mtc0    $2, $9
	MIPS32_NOP,						// nop

	// cp0 entryhi
	MIPS32_SW(2, 40, 1),			// lw      $2, 40($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 10, 0),			// mtc0    $2, $10
	MIPS32_NOP,						// nop

	// cp0 reg11
	MIPS32_SW(2, 44, 1),			// lw      $2, 44($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 11, 0),			// mtc0    $2, $11
	MIPS32_NOP,						// nop

	// cp0 reg12
	MIPS32_SW(2, 48, 1),			// lw      $2, 48($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 12, 0),			// mtc0    $2, $12
	MIPS32_NOP,						// nop

	// cp0 reg13
	MIPS32_SW(2, 52, 1),			// lw      $2, 52($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 13, 0),			// mtc0    $2, $13
	MIPS32_NOP,						// nop

	// cp0 reg14
	MIPS32_SW(2, 56, 1),			// lw      $2, 56($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 14, 0),			// mtc0    $2, $14
	MIPS32_NOP,						// nop

	// cp0 prid
	MIPS32_SW(2, 60, 1),			// lw      $2, 60($1)
	MIPS32_NOP,						// nop
	MIPS32_MTC0(2, 15, 0),			// mtc0    $2, $15
	MIPS32_NOP,						// nop

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(77)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

//const ubase_t mips32_microcode_readdepc[];

const ubase_t mips32_microcode_writedepc[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// Load R1 with the address of the data register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFE94),		// ori		$1, $1, 0xFE94

	// load R2 @R1 into the data register
	MIPS32_SW(2, 0, 1),				// lw	    $2, 0($1)
	MIPS32_NOP,						// nop

	// Store R2 to the DEPC register (CP0 reg 24 select 0)
	MIPS32_MTC0(2, 24, 0),			// mtc0		$2, $24
	MIPS32_NOP,						// nop

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(17)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readbytes[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)
	MIPS32_SW(4, 0, 15),			// sw	    $4, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($1)       # start address
	MIPS32_LW(3, 4, 15),			// lw	    $3, 4($1)       # end address

	// Hosted virtual ram base address
	MIPS32_LUI(4, 0xFF2F),			// lui		$4, 0xFF2F
	MIPS32_ORI(4, 4, 0x0000),		// ori		$4, $4, 0x0000

//1:
	MIPS32_LBU(1, 0, 2),			// lbu		$1, 0($2)
	MIPS32_ADDI(2, 2, 0x01),		// addiu	$2, $2, 0x01
	MIPS32_SB(1, 0, 4),				// sb		$1, 0($4)
	MIPS32_BNE(3, 2, NEG16(3)),		// bne		$3, $2, 1b      # if $3 != $2, goto 1b
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(4, 0, 15),			// lw	    $4, 0($15)
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(24)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writebytes[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)
	MIPS32_SW(4, 0, 15),			// sw	    $4, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($1)       # start address
	MIPS32_LW(3, 4, 15),			// lw	    $3, 4($1)       # end address

	// Hosted virtual ram base address
	MIPS32_LUI(4, 0xFF2F),			// lui		$4, 0xFF2F
	MIPS32_ORI(4, 4, 0x0000),		// ori		$4, $4, 0x0000

//1:
	MIPS32_LBU(1, 0, 4),			// lbu		$1, 0($4)
	MIPS32_NOP,						// nop
	MIPS32_SB(1, 0, 2),				// sb		$1, 0($2)
	MIPS32_ADDI(2, 2, 0x01),		// addiu	$2, $2, 0x01
	MIPS32_BNE(3, 2, NEG16(4)),		// bne		$3, $2, 1b      # if $3 != $2, goto 1b
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(4, 0, 15),			// lw	    $4, 0($15)
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(25)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readhalfs[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)
	MIPS32_SW(4, 0, 15),			// sw	    $4, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($1)       # start address
	MIPS32_LW(3, 4, 15),			// lw	    $3, 4($1)       # end address

	// Hosted virtual ram base address
	MIPS32_LUI(4, 0xFF2F),			// lui		$4, 0xFF2F
	MIPS32_ORI(4, 4, 0x0000),		// ori		$4, $4, 0x0000

//1:
	MIPS32_LHU(1, 0, 2),			// lhu		$1, 0($2)
	MIPS32_ADDI(2, 2, 0x01),		// addiu	$2, $2, 0x01
	MIPS32_SH(1, 0, 4),				// sh		$1, 0($4)
	MIPS32_BNE(3, 2, NEG16(3)),		// bne		$3, $2, 1b      # if $3 != $2, goto 1b
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(4, 0, 15),			// lw	    $4, 0($15)
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(24)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writehalfs[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)
	MIPS32_SW(4, 0, 15),			// sw	    $4, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($1)       # start address
	MIPS32_LW(3, 4, 15),			// lw	    $3, 4($1)       # end address

	// Hosted virtual ram base address
	MIPS32_LUI(4, 0xFF2F),			// lui		$4, 0xFF2F
	MIPS32_ORI(4, 4, 0x0000),		// ori		$4, $4, 0x0000

//1:
	MIPS32_LHU(1, 0, 4),			// lhu		$1, 0($4)
	MIPS32_NOP,						// nop
	MIPS32_SH(1, 0, 2),				// sh		$1, 0($2)
	MIPS32_ADDI(2, 2, 0x01),		// addiu	$2, $2, 0x01
	MIPS32_BNE(3, 2, NEG16(4)),		// bne		$3, $2, 1b      # if $3 != $2, goto 1b
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(4, 0, 15),			// lw	    $4, 0($15)
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(25)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readwords[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)
	MIPS32_SW(4, 0, 15),			// sw	    $4, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($1)       # start address
	MIPS32_LW(3, 4, 15),			// lw	    $3, 4($1)       # end address

	// Hosted virtual ram base address
	MIPS32_LUI(4, 0xFF2F),			// lui		$4, 0xFF2F
	MIPS32_ORI(4, 4, 0x0000),		// ori		$4, $4, 0x0000

//1:
	MIPS32_LW(1, 0, 2),				// lw		$1, 0($2)
	MIPS32_ADDI(2, 2, 0x01),		// addiu	$2, $2, 0x01
	MIPS32_SW(1, 0, 4),				// sw		$1, 0($4)
	MIPS32_BNE(3, 2, NEG16(3)),		// bne		$3, $2, 1b      # if $3 != $2, goto 1b
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(4, 0, 15),			// lw	    $4, 0($15)
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(24)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writewords[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)
	MIPS32_SW(4, 0, 15),			// sw	    $4, 0($15)

	// Load R1 with the address of the address register
	MIPS32_LUI(1, 0xFF2F),			// lui	    $1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD00),		// ori	    $1, $1, 0xFD00
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($1)       # start address
	MIPS32_LW(3, 4, 15),			// lw	    $3, 4($1)       # end address

	// Hosted virtual ram base address
	MIPS32_LUI(4, 0xFF2F),			// lui		$4, 0xFF2F
	MIPS32_ORI(4, 4, 0x0000),		// ori		$4, $4, 0x0000

//1:
	MIPS32_LW(1, 0, 4),				// lw		$1, 0($4)
	MIPS32_NOP,						// nop
	MIPS32_SW(1, 0, 2),				// sw		$1, 0($2)
	MIPS32_ADDI(2, 2, 0x01),		// addiu	$2, $2, 0x01
	MIPS32_BNE(3, 2, NEG16(4)),		// bne		$3, $2, 1b      # if $3 != $2, goto 1b
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(4, 0, 15),			// lw	    $4, 0($15)
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(25)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readibs[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// IBS in drseg of target
	MIPS32_LUI(1, 0xFF30),			// lui	    $1, 0xFF30
	MIPS32_ORI(1, 1, 0x1000),		// ori	    $1, $1, 0x1000
	MIPS32_LW(2, 0, 1),				// lw		$2, 0($1)

	// Hosted memory address
	MIPS32_LUI(1, 0xFF2F),			// lui		$1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori		$1, $1, 0xFD04
	MIPS32_SW(2, 0, 1),				// sw		$2, 0($1)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(18)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writeibs[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// Hosted virtual address
	MIPS32_LUI(1, 0xFF2F),			// lui		$1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori		$1, $1, 0xFD04
	MIPS32_SW(2, 0, 1),				// lw		$2, 0($1)

	// IBS in DSREG of target
	MIPS32_LUI(1, 0xFF30),			// lui	    $1, 0xFF30
	MIPS32_ORI(1, 1, 0x1000),		// ori	    $1, $1, 0x1000
	MIPS32_SW(2, 0, 1),				// sw	    $2, 0($1)
	MIPS32_NOP,						// nop

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(18)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readdbs[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// commit access
	// sync
	MIPS32_NOP,						// nop

	// IBS in DSREG of target
	MIPS32_LUI(1, 0xFF30),			// lui	    $1, 0xFF30
	MIPS32_ORI(1, 1, 0x1000),		// ori	    $1, $1, 0x1000
	MIPS32_LW(2, 0, 1),				// lw		$2, 0($1)

	// Hosted virtual address
	MIPS32_LUI(1, 0xFF2F),			// lui		$1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori		$1, $1, 0xFD04
	MIPS32_SW(2, 0, 1),				// sw	    $2, 0($1)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(18)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writedbs[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// Hosted virtual address
	MIPS32_LUI(1, 0xFF2F),			// lui		$1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori		$1, $1, 0xFD04
	MIPS32_LW(2, 0, 1),				// lw      $2, 0($1)

	// IBS in DSREG of target
	MIPS32_LUI(1, 0xFF30),			// lui	    $1, 0xFF30
	MIPS32_ORI(1, 1, 0x1000),		// ori	    $1, $1, 0x1000
	MIPS32_SW(2, 0, 1),				// sw	    $2, 0($1)
	MIPS32_NOP,						// nop

	// commit access
	// sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(18)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writehwbkpt[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)

	MIPS32_LUI(3, 0xFF2F),			// lui		$3, 0xFF2F
	MIPS32_ORI(3, 3, 0xFD00),		// ori		$3, $3, 0xFD00
	// Hosted memory address of hardware breakpoint register
	MIPS32_LW(1, 0, 3),				// lw		$1, 0($3)
	// Target address of hardware breakpoint register
	MIPS32_LW(1, 4, 3),				// lw		$2, 4($3)

	// IBA
	MIPS32_LW(3, 0, 1),				// lw	    $3, 0($1)
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 0, 2),				// sw		$3, 0($2)
	MIPS32_NOP,						// nop

	// IBM
	MIPS32_LW(3, 4, 1),				// lw	    $3, 4($1)
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 8, 2),				// sw		$3, 8($2)
	MIPS32_NOP,						// nop

	// IBASID
	MIPS32_LW(3, 8, 1),				// lw	    $3, 8($1)
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 16, 2),			// sw		$3, 16($2)
	MIPS32_NOP,						// nop

	// IBC
	MIPS32_LW(3, 12, 1),			// lw	    $3, 12($1)
	MIPS32_NOP,						// nop
	MIPS32_SW(3, 24, 2),			// sw		$3, 24($2)
	MIPS32_NOP,						// nop

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(33)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writehwwpt[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)
	MIPS32_SW(3, 0, 15),			// sw	    $3, 0($15)

	MIPS32_LUI(3, 0xFF2F),			// lui		$3, 0xFF2F
	MIPS32_ORI(3, 3, 0xFD00),		// ori		$3, $3, 0xFD00
	// Hosted memory address of hardware watchpoint register
	MIPS32_LW(1, 0, 3),				// lw		$1, 0($3)
	// Target address of hardware watchpoint register
	MIPS32_LW(1, 4, 3),				// lw		$2, 4($3)

	// DBA
	MIPS32_LW(3, 0, 1),				// lw	    $3, 0($1)
	MIPS32_NOP,						// nop
	MIPS32_LW(3, 0, 2),				// sw		$3, 0($2)
	MIPS32_NOP,						// nop

	// DBM
	MIPS32_LW(3, 4, 1),				// lw	    $3, 4($1)
	MIPS32_NOP,						// nop
	MIPS32_LW(3, 8, 2),				// sw		$3, 8($2)
	MIPS32_NOP,						// nop

	// DBASID
	MIPS32_LW(3, 8, 1),				// lw	    $3, 8($1)
	MIPS32_NOP,						// nop
	MIPS32_LW(3, 16, 2),			// sw		$3, 16($2)
	MIPS32_NOP,						// nop

	// DBC
	MIPS32_LW(3, 12, 1),			// lw	    $3, 12($1)
	MIPS32_NOP,						// nop
	MIPS32_LW(3, 24, 2),			// sw		$3, 24($2)
	MIPS32_NOP,						// nop

	// DBV
	MIPS32_LW(3, 16, 1),			// lw	    $3, 16($1)
	MIPS32_NOP,						// nop
	MIPS32_LW(3, 32, 2),			// sw		$3, 32($2)
	MIPS32_NOP,						// nop

	// DBVHi
//	MIPS32_LW(3, 20, 1),			// lw	    $3, 20($1)
//	MIPS32_NOP,						// nop
//	MIPS32_LW(3, 36, 2),			// sw		$3, 36($2)
//	MIPS32_NOP,						// nop

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(3, 0, 15),			// lw	    $3, 0($15)
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(36)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_readcpx[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// load the vm address of ui_data_register
	MIPS32_LUI(1, 0xFF2F),			// lui		$1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori		$1, $1, 0xFD04

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// the below instruction will be changed dynamically
	MIPS32_MTC0(2, 0, 0),			// mfc0    $2, $0
	MIPS32_NOP,						// nop
	MIPS32_SW(2, 0, 1),				// sw		$2, 0($1)
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(36)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_writecpx[] = 
{
// start:
	// $15 as the debug stack pointer
	MIPS32_MTC0(15, 31, 0),			// mtc0		$15, $31
	MIPS32_LUI(15, 0xFF2F),			// lui	    $15, 0xFF2F
	MIPS32_ORI(15, 15, 0xFFFC),		// ori	    $15, $15, 0xFFFC

	// Push to the debug stack
	MIPS32_SW(1, 0, 15),			// sw	    $1, 0($15)
	MIPS32_SW(2, 0, 15),			// sw	    $2, 0($15)

	// load the vm address of ui_data_register
	MIPS32_LUI(1, 0xFF2F),			// lui		$1, 0xFF2F
	MIPS32_ORI(1, 1, 0xFD04),		// ori		$1, $1, 0xFD04

	MIPS32_SW(2, 0, 1),				// lw		$2, 0($1)
	MIPS32_NOP,						// nop
	// the below instruction will be changed dynamically
	MIPS32_MTC0(2, 0, 0),			// mtc0		$2, $0
	MIPS32_NOP,						// nop

	// commit access
	//sync
	MIPS32_NOP,						// nop

	// Pop from debug stack
//pop_debug_stack:
	MIPS32_LW(2, 0, 15),			// lw	    $2, 0($15)
	MIPS32_LW(1, 0, 15),			// lw	    $1, 0($15)

	// Restore R15 from the scratch register
	MIPS32_MFC0(15, 31, 0),			// mfc0		$15, $31

	MIPS32_B(NEG16(36)),			// beq		$0, $0, start
	MIPS32_NOP,						// nop
	0x0000001C,						// .word	pop_debug_stack		# remember the pop stack instruction address
};

const ubase_t mips32_microcode_dbgexceprtn[] = 
{
	// read the cause to determine what happens
	MIPS32_MFC0(1, 23, 0),			// mfc0		$1, $23, 0
	MIPS32_ORI(2, 0, 0x7C00),		// ori		$2, $0, 0x7C00
	MIPS32_AND(1, 1, 2),			// and		$1, $1, $2

	// load the saved depc
	MIPS32_LUI(2, 0xFF2F),			// lui	    $2, 0xFF2F
	MIPS32_ORI(2, 2, 0xFD00),		// ori	    $2, $2, 0xFD00
	MIPS32_SW(1, 8, 2),				// sw		$1, 8($2)		# tell boss what happened
	MIPS32_NOP,						// nop
	MIPS32_NOP,						// nop
	MIPS32_LW(1, 0, 2),				// lw		$1, 0($2)		# depc to restore
	MIPS32_NOP,						// nop
	MIPS32_MFC0(1, 24, 0),			// mtc0		$1, $24, 0		# restore depc
	MIPS32_NOP,						// nop
	MIPS32_SW(1, 4, 2),				// lw		$1, 4($2)		# the pc address where to jump to
	MIPS32_NOP,						// nop

	// jump to where cause debug exception
	MIPS32_JR(1),					// jr		$1
	MIPS32_NOP,						// nop
};

const ubase_t mips32_microcode_flushicache[] = 
{
	MIPS32_NOP,
};

const ubase_t mips32_microcode_flushdcache[] = 
{
	MIPS32_NOP,
};

const ubase_t mips32_microcode_flushicacherange[] = 
{
	MIPS32_NOP,
};

const ubase_t mips32_microcode_flushdcacherange[] = 
{
	MIPS32_NOP,
};

const ubase_t mips32_microcode_synci[] = 
{
	MIPS32_NOP,
};

const ubase_t mips32_microcode_readitag[] = 
{
	MIPS32_NOP,
};

const ubase_t mips32_microcode_readdtag[] = 
{
	MIPS32_NOP,
};

const ubase_t mips32_microcode_readtlb[] = 
{
	MIPS32_NOP,
};

const ubase_t mips32_microcode_writetlb[] = 
{
	MIPS32_NOP,
};

